Differential emitter-coupled logic buffer having reduced power dissipation
US6552577B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic buffer includes a logic gate having at least two input terminals and two output nodes, a plurality of output terminals, each having a capacitance associated therewith and a pull-up circuit interconnected between each output node and the plurality of output terminals for alternately charging the capacitance of each output terminal. The buffer also includes a differential pull-down circuit including a common pull-down current source, the pull-down device interconnected between the output nodes and the output terminals for inversely alternately discharging the capacitances through the common pull-down current source for accelerating the discharge of the capacitance of the respective output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.