Power down circuit detecting duty cycle of input signal
US6552578B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2002 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jun 10, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
When the clock is stopped during a power-down mode, a clock duty-cycle detector asserts a power-down signal. The clock input is filtered to produce an average clock voltage over several clock periods. The average clock voltage is compared to an upper reference voltage to determine when the clock's duty cycle (high pulse-width percent) is above an upper limit. The average clock voltage is also compared to a lower reference voltage to determine when the clock's duty cycle is below a lower limit. When the clock's duty cycle is above the upper limit or below the lower limit the power-down signal is activated by logic. The logic disables the power-down signal when the clock's duty cycle is between the upper and lower limits. High-frequency clock glitches do not falsely trigger a power-up, since glitches are usually narrow and not sufficiently wide to reach the lower limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.