Source follower for low voltage differential signaling
US6552582B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Sep 27, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A source follower circuit for low voltage differential signaling (LVDS) has a low power consumption, low noise, and the ability to drive a highly capacitive load at an output port of an integrated circuit (IC). The source follower circuit includes a first p-channel transistor having a drain coupled to a supply voltage and a gate coupled to a first input; a second p-channel transistor having a drain coupled to the supply voltage and a gate coupled to a second input which is complementary to the first input; a third p-channel transistor having a gate coupled to the second input, a source coupled to ground, and a drain coupled to a source of the first p-channel transistor which forms a first output; and a fourth p-channel transistor having a source coupled to the ground and a drain coupled to a source of the second p-channel transistor which forms a second output which is complementary to the first output. Advantageously, the output signals of the circuit are referenced to ground and are less affected by power supply variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.