Biasing of a mixer
US6552586B2 · kind B2 · utility
5Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Sep 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A mixer including a stage for inputting a voltage signal to be shifted and a shift and output stage for providing frequency-shifted signals, a biasing network of the output stage including, between a high supply and a biasing node, a constant current source in parallel with an output element of a current mirror, an input element of which receives a bias order from the input stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.