Clocking scheme for ASIC
US6552590B2 · kind B2 · utility
1Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jun 13, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock scheme for a system on a chip wherein integral sub-multiples of a system clock have positive edges on odd-numbered positive edges of the system clock and negative edges on even-numbered positive edges Data transfer between blocks of different frequencies is controlled by a state machine of the higher frequency block and can be achieved without elastic buffers and/or synchronizers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.