Asynchronous phase detector for a PLD independent of timing requirements
US6552616B1 · kind B1 · utility
2Cited by
3References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Mar 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.