Processor with pulse width modulation generator with fault input prioritization
US6552625B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/34217
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor. A pulse width modulation generator for a processor includes fault priority circuitry having a plurality of fault inputs operable to receive fault input signals and a fault output operable to output a fault output signal, the fault priority circuitry operable to receive fault input signals on a plurality of fault inputs concurrently, and output a fault output signal corresponding to a fault input having a highest priority among the fault inputs that are receiving fault input signals, and pulse width modulation circuitry having at least one pulse width modulation output operable to output at least one pulse width modulated signal and a fault input operable to receive the fault output signal from the fault priority circuitry, the pulse width modulation circuitry operable to drive the pulse width modulation output to a defined state associated with the selected fault input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.