Configurable vertex blending circuit and method therefore
US6552733B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Apr 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A configurable vertex blending circuit that allows both morphing and skinning operations to be supported in dedicated hardware is presented. Such a configurable vertex blending circuit includes a matrix array that is used for storing the matrices associated with the various portions of the vertex blending operations. Vertex data that is received is stored in an input vertex buffer that includes multiple position buffers such that the multiple positions associated with morphing operations can be stored. Similarly, the single position typically associated with skinning operations can be stored in one of the position buffers. The input vertex buffer further stores blending weights associated with the various component operations that are included in the overall vertex blending operation. An arithmetic unit, which is configured and controlled by a transform controller, performs the calculations required for each of a plurality of component operations included in the overall vertex blending operation. The results of each of these component operations are then combined to produce a blended vertex.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.