Active Vcc-to-Vss ESD clamp with hystersis for low supply chips

US6552886B1 · kind B1 · utility

Assignee

• Pericom Semiconductor Corporation · US

Inventors

• Ke Wu · Montréal, CA
• David Kwong · Fremont, US

Key dates

• Filing date: Jun 29, 2000
• Grant date: Apr 22, 2003
• Expiry date: Aug 8, 2021

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/819

Abstract

An electro-static-discharge (ESD) protection circuit is coupled between power and ground. It protects core circuits in a semiconductor chip. The ESD protection circuit is an active circuit that drives the gate of an n-channel clamp transistor. The clamp transistor shunts current from power to ground when its gate is driven high during an ESD event. A voltage divider generates a sense voltage that drives a first inverter. The sense voltage is normally much lower than the switch threshold of the first inverter. When an ESD voltage spike occurs, the sense voltage rises above the switch threshold, switching the output of the first inverter. A string of inverters is driven by the first inverter, with a final inverter driving the gate of the clamp transistor. An extending n-channel transistor drives the input of the final inverter low when the clamping transistor is on, extending the discharge time. A hysteresis p-channel transistor drives the output of the first inverter high, delaying turn-on of the clamp transistor. This increases the voltage required to trigger the protection circuit.