Method and apparatus for identifying SRAM cells having weak pull-up PFETs
US6552941B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jul 11, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for determining the memory cell stability of individual memory cells included within a memory array is disclosed. In an exemplary embodiment, the method includes presetting each memory cell to a first logic state and then applying a gradually increasing, controlled leakage current to a node within each memory cell. The voltage of each of the nodes within each corresponding memory cell is then monitored. Then, for each memory cell within the memory array, the level of leakage current which causes the memory cell to be changed from the first logic state to a second logic state is determined. The level of leakage current which causes the memory cell to be changed from the first logic state to the second logic state corresponds to the threshold voltage of a pull-up PFET within the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.