Data line precharging circuit of a semiconductor memory device
US6552942B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jun 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has at least one data line, registers for storing data bits, and switch elements corresponding to the registers for transferring the data bits to the data line in response to corresponding selection signals. It also has a precharge circuit connected to the data line, for precharging the data line to a power supply voltage in response to a precharge control signal. The selection signals are sequentially activated at a predetermined time interval by synchronously responding to a clock signal, and the precharge control signal is activated during the interval of the selection signals, by synchronously responding to the clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.