Reducing leakage current in a memory device
US6552949B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2002 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Feb 5, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory device and method for reducing leakage current during a power down mode of operation. The memory device comprises a column of memory cells, with each memory cell being arranged to store a data value, and a pair of bit lines coupled to the column of memory cells. Bit line precharge circuitry is provided for precharging the pair of bit lines to a predetermined voltage level during a precharge phase, the pair of bit lines being arranged such that, when a particular memory cell in the column is selected in an evaluate phase following the precharge phase, a relative change in voltage level between the pair of bit lines indicates the data value stored within the selected memory cell. In accordance with the present invention, the memory device further comprises power down control circuitry arranged when the memory device is to enter a power down mode to prevent the bit line precharge circuitry from precharging the pair of bit lines, and selector circuitry arranged when the memory device is to enter the power down mode to ensure that none of the memory cells in the column are selected. It has been found that by taking this approach during the power…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.