Nonvolatile semiconductor memory device having changeable spare memory address
US6552950B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 28, 2001 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Jan 17, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a method thereof are disclosed. The logical addresses of the spare memory cell array are assigned prior to the logical addresses of the main memory cell array in response to a first control signal, and data stored in the spare memory cell array is read earlier than data in the main memory cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.