Timing optimization in presence of interconnect delays
US6553338B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 1999 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Apr 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A strategy for optimal buffering in the case of an infinitely long wire buffered with an arbitrary number of equally spaced single-size buffers is presented. A simple but efficient technique is proposed using this to choose a buffer size and determine a good inter-buffering distance up front, thus enabling fast, efficient buffer insertion. The analysis also allows representing delays of long wires as a simple function of the length and buffer and wire widths. Based on this, a novel constant wire delay approach is proposed where the proposed wire delay model is used for fairly accurate prediction of wire delays early in the design process and these predictions are later met via buffer insertion and wire sizing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.