Circuitry, architecture and method(s) for synchronizing data
US6553503B1 · kind B1 · utility
5Cited by
10References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.