Method and apparatus for performing clock timing de-skew
US6553505B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 29, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Feb 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention provides a method for performing timing de-skew in order to properly receive digital computer information. A sequence of N clock pulses are generated at intervals having phases offset from one another by T/N, where N is at least 2, T is a duration of one bit-cell time, and one cycle of each of the clock phases has a duration of 2T. A test signal is generated at a transmitting portion. The test signal is received, and one of the generated sequences of clock pulses which is aligned with the test signal is identified. The identified one of the generated sequences of clock pulses is used to determine which one of the generated sequences of clock pulses and which polarity to use to receive data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.