Method and apparatus for resolving CPU deadlocks
US6553512B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Apr 22, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for handling errors that deadlock a CPU by first attempting to resolve the deadlock without issuing a bus error and without restarting the CPU. If the deadlock cannot be resolved without issuing a bus error, then a bus error is issued and the CPU attempts to restart. The method involves comparing the number of clock cycles taken to execute an instruction to a designated abort value. When an instruction has taken the full abort value of cycles but has not retired, a machine-check abort (MCA) is issued to attempt to resolve the deadlock. The method also involves comparing the number of clock cycles to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the machine attempts to reset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.