Multi-layer printed circuit board and method of making same
US6555015B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Nov 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/4685
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Method of manufacturing a multi-layer printed circuit board adapted for reduce interfacial sheer stresses includes a laminate substrate having a top layer forming a first major surface, a middle layer having a predetermined thickness and a bottom layer forming a second major surface opposed to the first major surface. Etch resists are disposed on the first and second surfaces corresponding to reverse images of desired conductor patterns. The first and second surfaces are thereafter etched and the photoresist removed. The laminate substrate is secured via a low modules adhesive layer to a major surface of a base. The middle layer of the laminate substrate is thereafter selectively etched so as to isolate selected portions of the first and second surfaces and to define inner connect regions therebetween having a height equal to the predetermined thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.