Latch structures and systems with enhanced speed and reduced current drain
US6556060B1 · kind B1 · utility
6Cited by
9References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 2002 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jun 6, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356104
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Latch structures and systems are disclosed that enhance latch speed and reduce latch current drain while providing complementary metal-oxide-semiconductor (CMOS)-level latch signals. They are realized with bipolar junction structures and CMOS structures that are arranged to limit latch currents in response to CMOS-level sense signals Ssns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.