Patent · US Expired

Phase-locked loop having a stable damping factor

US6556088B1 · kind B1 · utility

12Cited by
1References
7Claims
0Family size

Assignee

Inventors

Key dates

Filing dateOct 12, 2000
Grant dateApr 29, 2003
Priority date
Expiry dateOct 12, 2020

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L2207/04
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A phase-locked loop (PLL) has a phase detector coupled to an output of the PLL and to a reference signal and a low pass filter including a first and a second charge pump coupled to an output of the phase detector. A capacitor is coupled to an output of the first charge pump, a first bias circuit coupled to the capacitor, the first bias circuit having a differential output. A voltage controlled ring oscillator has a plurality of differential inventer stages, each having a first input coupled to a first output of the first bias circuit and a second input coupled to a second output of the first bias circuit. A second bias circuit is coupled between the capacitor and the first bias circuit, an output of the second bias circuit being coupled to an input of the first bias circuit and to an output of the second charge pump. The PLL circuit exhibits a stable damping factor with respect to frequency.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.