Offset voltage calibration DAC with reduced sensitivity to mismatch errors
US6556154B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1998 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Oct 25, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/68
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A composite digital-to-analog converter (DAC) includes a first DAC and a second DAC. The first DAC has a first range and a first error. The second DAC has a second range and a second error. The second range of the second DAC is less than the first range of the first DAC. The second range of the second DAC is greater than the first error of the first DAC. The second error of the second DAC is less than the first error of the first DAC. The composite DAC has a composite range and a composite error. The second DAC is coupled to minimize the composite error such that the composite range of the composite DAC is the first range and the composite error of the composite DAC is the second error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.