Jitter cancellation technique for video clock recovery circuitry
US6556249B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Sep 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N9/89
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for compensating for time base or phase errors in video and audio signals that are separately stored or processed. A ring oscillator provides a plurality of clock signals, each having a same frequency and slightly different phase. Each of the clock signals is applied to a multiplexor for allowing an appropriate one of the clock signals to be selected. By selecting appropriate ones of the clock signals in a sequence, the frequency and phase of an output clock signal formed by the multiplexor can be continuously and precisely controlled. Sync pulses separated from a video signal having a varying time base are applied to a video timing generator circuit which generates a series of digital values representative of timing differences between an expected occurrence of a sync pulse and an actual occurrence of the sync pulse. A phase accumulator accumulates the digital values over time for generating appropriate addresses for the multiplexor. Therefore, the frequency and phase of the output clock signal is controlled according to the phase of the sync pulses. Additional logic circuits coupled to the video timing generator generate a series of digital values represent…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.