Demultiplexing and clock-recovery circuit
US6556323B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Feb 16, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0075
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An optical element for simultaneously retrieving the tributary data rate and the clock frequency from the line rate of an OTDM signal. The demultiplexing and clock recovery principle is based on injection locking of a high-Q-filtered and high gain loop with a variable phase delay and an EA-modulator with high non-linear response, i.e., absorption verses applied voltage. A modulator that is preferably an EA-modulator, an amplifier preferably an erbium doped fiber amplifier (“EDFA”), a base band receiver, an electronic amplifier, a high-Q filter, and a variable phase delay are arranged in a loop to provide an oscillator for simultaneously retrieving tributary data rate and clock frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.