Dielectric ceramic composition, multi-layer ceramic capacitor using the same, and manufacturing method therefor
US6556422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | May 18, 2021 |
Classification
- Technology area (CPC C)Chemistry; Metallurgy
- CPC primaryC04B2235/3418
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A dielectric ceramic composition, a multi-layer ceramic capacitor and a manufacturing method characterized by superior dielectric properties. The ceramic capacitor includes a chip having a plurality of dielectric layers, a plurality of internal electrodes stacked alternately with the dielectric layers, and a pair of outer electrodes formed on both sides of the chip, with the composition of the dielectric layers including: 100 moles of barium calcium titanate BaCaxTiO3 (0.001≦x≦0.02), 0.5-4 moles of MgO, 0.01-0.5 moles of MnO, 0.1—2 moles of BaO, 0.1-2 moles of CaO, 1-4 moles of SiO2, and 0.1-3 moles of at least one or more compounds selected from the group consisting of Y2O3, Dy2O3, Ho203 and Er2O3. The capacitor thus manufactured satisfies the X7R standard and has superior dielectric properties, and the deviations of the dielectric properties are extremely low, thereby ensuring a high reliability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.