VDD modulated SRAM for highly scaled, high performance cache
US6556471B2 · kind B2 · utility
45Cited by
2References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jun 27, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a device and method for fast SRAM reading and writing. A boost voltage source is provided, wherein the boost voltage source operates to increase a conductance of a latch device in the SRAM cell relative to a conductance of an access device in the SRAM cell. By virtue of the increased relative conductance between the latch and access devices (beta ratio), the access device may be assume a wider width without jeopardizing the read stability of the cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.