2-D FIFO memory having full-width read/write capability
US6556495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jul 9, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.