Frequency multiplier circuit and method using above circuit for a period time division in subperiods, for a brushless motor
US6556644B2 · kind B2 · utility
0Cited by
4References
16Claims
0Family size
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Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Jun 1, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier circuit and a controlling method thereof, which measures a period of a waveform by counting cycles of a fixed frequency timing signal, and reproduces the period by adding a number of prefixed length subperiods of the fixed frequency to the cycle count, making it as equal as possible to the period, so to minimize the reproduction error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.