Shift register
US6556646B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1999 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Aug 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register for driving a pixel row in a liquid crystal display device. In the shift register, a plurality of stages are connected to a high level voltage source, a low level voltage source and a phase-delayed clock signal generator, connected to row lines, and connected, in cascade, with respect to a scanning signal, for charging and discharging the row lines. In each stage of the shift register, an output circuit is provided with a pull-up transistor having a first input electrode for receiving a first clock signal having a delayed phase in comparison to the scanning signal, a first output electrode connected to the raw line and a first control electrode, and a pull-down transistor having a second input electrode connected to the low level voltage source, a second output electrode connected to the row line and a second control electrode. An input circuit responds to the scanning signal to generate a first control signal to be applied to the first control electrode, and responds to a second clock signal having a delayed phase in comparison to the first clock signal to generate a second control signal to be applied to the second control electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.