On-the-fly compression for pixel data
US6556716B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Mar 31, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/523
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video signal processor operates an arithmetic logic unit to perform on-the-fly compression of image data as the image data is input to the processor. The on-the-fly compression provides a data input pipeline that stores compressed image data for a large image area in a relatively small buffer in the processor. A hierarchical motion estimation process can first search the large image area by comparing blocks of the compressed image data to a compressed reference block. The hierarchical search process can then store uncompressed image data for a smaller image area and search the smaller image area to accurately determine a motion vector for the reference block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.