Digital signal processor with coupled multiply-accumulate units
US6557022B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Feb 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two multiply-accumulate units are coupled together so that the computation (B*C)+(D*E) can be completed in one cycle. An adder (216) adds together the products of the two multipliers (206), (208). The sum is applied to the first accumulator (220). Preferably, the second product is also applied to the second accumulator (222), and a multiplexer (218) applies either a zero or the second product to the adder (216). If two unrelated computations are to be executed simultaneously, then the zero is applied, and the output of the second accumulator is fed back to the register file (PI2). If a single (B*C)+(D*E) computation is to be executed, then the second product is applied to the adder, and the output of the second accumulator is disregarded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.