CPU expandability bus
US6557065B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1999 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Dec 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide a computer system with a high speed, high bandwidth expandability bus for integrated and non-integrated CPU products. The computer system includes a processor, a chipset coupled to the processor, a graphics processor coupled to the chipset for controlling a video display and a main memory coupled to the chipset. The computer system further includes an expandability bus, which is coupled at one end to the chipset and at the other end to a replaceable electronic component. The expandability bus can be changeably configured to enable or disable bus mastering at both ends, as required, to operate with whichever replaceable electronic component is installed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.