Method and system for fault isolation for PCI bus errors
US6557121B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Aug 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and system aspects for fault isolation on a bus are provided. In a method aspect, a method for isolating a fault condition on a bus of a computer system, the computer system including an input/output (I/O) subsystem formed by a plurality of I/O devices communicating via the bus, includes categorizing, in a recursive manner, the I/O subsystem, and isolating a source of an error condition within the I/O subsystem. Further, the I/O subsystem communicates via a peripheral component interconnect, PCI, bus. In a system aspect, a computer system for isolating a fault condition on a PCI bus includes a processing mechanism, and an input/output mechanism, coupled to the processing mechanism, comprising a plurality of input/output devices and bridges coupled to a PCI bus and communicating according to a PCI standard. In addition, the system includes a fault isolation mechanism within the processing mechanism for identifying a source of an error condition in the input/output mechanism. Further, the fault isolation mechanism performs categorization of the input/output mechanism in a recursive manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.