Method for correction of errors in a binary word stored in multi-level memory cells, with minimum number of correction bits
US6557138B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 9, 2000 |
| Grant date | Apr 29, 2003 |
| Priority date | — |
| Expiry date | Feb 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for correction of errors in a word stored in multi-bit memory cells includes associating a full error code, which includes bit error codes and a set error code, for each set of bits of the word stored in a single memory cell. The method includes associating, with each single error, a bit error code which is not associated with other errors and which is indicative of a position of the bit in the word. The set error code is computed based on the bit error codes associated with the bits in the set. The method also checks to make sure that the full error code for the set has not already been associated with other errors. If the error code has already been used for another error, then the method changes both the set error code and at least one of the bit error codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.