SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
US6558998B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Feb 15, 2002 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Feb 15, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit comprising:at least one first and one second power supply terminal (418, 420),at least one active area (302, 304, 306, 308) formed in a thin layer (206) of a substrate and electrically connected to at least one of the power supply terminals.According to the invention, the circuit also comprises capacitive decoupling means formed by at least one dielectric capacitor (110, 112, 114) connected between the said, first and second power supply terminals and formed in a region of the substrate that is electrically insulated from the thin substrate layer (206).Applications include the manufacture of portable electronic equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.