Regenerative signal level converter
US6559685B2 · kind B2 · utility
62Cited by
4References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 16, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Apr 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35613
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and circuitry for converting a differential logic signal to a single-ended logic signal that minimize delay. In specific embodiments differential logic signals of the type employed in, for example, current-controlled complementary metal-oxide-semiconductor (C3MOS) logic are converted to single-ended rail-to-rail CMOS logic levels using the regenerative action of a
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.