Integrated circuit designs for high speed signal processing
US6559693B2 · kind B2 · utility
9Cited by
5References
20Claims
0Family size
Inventors
Key dates
| Filing date | May 2, 2002 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | May 2, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques designing an electronic circuit system including multiple transistors and passive components are presented. According to one aspect of the techniques, some or all of the transistors and passive components are systematically adjusted to minimize artifacts resulting from system-level interactions among these functional building blocks. The adjustment is based on a ratio of Electrically Equivalent Channel Geometry (EECG) of each of the adjusted the transistors and passive components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.