Method to reduce power bus transients in synchronous integrated circuits
US6559701B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jun 26, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing power rail transients on integrated circuits. The power rail transients are reduced by controlling clock skew in a manner which minimizes dI/dT current demands. The method provides that the phase of the clock to latches/flip flops is shifted in order to spread out the number of simultaneous switching elements. By controlling the number of simultaneous switching devices, a significant reduction in time rate of current demanded from the power rails can be achieved, thereby reducing the magnitude of VSS/VDD voltage transients due to parasitic inductances and resistances supplying power to the integrated circuit. Theoretically, the entire timing spread of the slack graph for clock skew can be used to control the number of simultaneous switching devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.