Apparatus for reducing charge kickback in a dynamic comparator
US6559787B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jul 23, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed a comparator comprising: 1) a first comparison circuit capable of receiving an input signal, wherein the first comparison circuit is enabled and compares the signal when a received LATCH signal is enabled and is disabled when the received LATCH signal is disabled; and 2) a second comparison circuit coupled to the input signal in parallel with the first comparison circuit, wherein an input stage of the second comparison circuit is substantially identical to an input stage of the first comparison circuit. The second comparison circuit is enabled and compares the input signal when the received LATCH is signal is disabled and is disabled when the received LATCH signal is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.