Memory cell decoder not including a charge pump
US6560162B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Nov 8, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell decoder includes a first node and a first transmitting portion adapted to output a high voltage signal to the first node responsive to a first selection signal. A control portion is adapted to generate a first control signal responsive to an address and discharge the first node responsive to the first control signal. A second transmitting portion is adapted to output a word line enable signal responsive to the first selection signal and the first control signal. A semiconductor memory device includes: a memory cell array having an array of memory cells; a plurality of word lines corresponding to the memory cells; a plurality of memory cell decoders adapted to select word lines responsive to an address; a first pre decoder adapted to decode the address and generate a plurality of block selection signals, the block selection signals selecting predetermined corresponding blocks in the memory cell decoders; a second pre decoder adapted to generate a plurality of word line enable signals responsive to the address, the word line enable signals for enabling corresponding word lines responsive to the address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.