DC offset correction scheme for wireless receivers
US6560447B2 · kind B2 · utility
52Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2001 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/061
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.