Method and system for controlling internal busses to prevent bus contention during internal scan testing
US6560663B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1999 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Sep 2, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/221
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.