Method and apparatus for reducing power consumption by skipping second accesses to previously accessed cache lines
US6560679B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2000 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Jun 16, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.