Power management for a peripheral component interconnect environment with auxiliary power
US6560714B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 3, 1999 |
| Grant date | May 6, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly. The first component conducts current from the first circuit subassembly when power is not available from the third power source and otherwise substantially does not conduct current. The second component is coupled to the third power source and the first compone…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.