Semiconductor device of multi-wiring structure and method of manufacturing the same
US6563218B2 · kind B2 · utility
9Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Nov 29, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.