Low-noise four-quadrant multiplier method and apparatus
US6563365B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Jan 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing noise in a four-quadrant multiplier having first and second cross-coupled pairs of differential bipolar transistors, differential input current terminals connected with a first pair of common junctions of the respective pairs of differential transistors and the differential output current terminals cross coupled to form a second pair of common junctions of the respective pairs of differential transistors is described. The method includes providing a noise current path from the differential input current terminals to a bias voltage, the noise current path substantially bypassing the differential output current terminals when the gain of the multiplier is near zero. Preferably, the first junctions are common emitter junctions and the second junctions are common collector junctions, and the noise current path comprises a third pair of transistors having respective emitters connected to the common emitter junctions, having common collectors connected to a bias voltage and common bases connected to a controlling voltage. Overall output noise is substantially reduced, as the current through the differential transistor pairs is shunted instead to the bias voltage, ef…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.