Method and structure for reducing noise effects in content addressable memories
US6563727B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Jul 31, 2002 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for reducing the coupling noise in a Content Addressable Memory (CAM), the CAM having a first bitline pair and a second bitline pair, both pairs aligned along a first axis; a first memory cell connected to the first bitline pair and a second memory cell to the second bitline pair; having a first match line and a first word line aligned along a second axis, the first match line and the first word line connecting the first and the second memory cells defining a first row in a first column; having a second row adjacent the first row, the second row comprising a third cell and a fourth cell, the third and fourth cells connecting the first and second bitline pairs and a second word line and a second match line, the method comprising arranging the first memory cell in a first orientation and the second memory cell in a second orientation, wherein the second orientation being a first axis mirror image to the first orientation; segmenting the first and second bitline pairs between the first row and the second row; adding a first twisting structure to the first bitline pair and a second twisting structure to the second bitline pair; arranging the third cell in a third orientation, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.