DRAM circuit with separate refresh memory
US6563754B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Dec 3, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/046
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A DRAM circuit including a first DRAM array used solely for refresh operations, and the second DRAM array for performing logic operations that is refreshed using data read from the first DRAM array. Specifically, data is read only from the first DRAM array during a read phase of the refresh operation, and is written to both the first DRAM array and the second DRAM array during the write phase of the refresh operation. Accordingly, the second DRAM array is able to simultaneously perform any type of logic operation without delay or disturbance caused by accessing the second DRAM array during the read phase. In one embodiment, the second DRAM array includes DRAM CAM cells that perform data matching operations using the data refreshed from the first DRAM array, which includes conventional DRAM memory cells. During read operations, because the data values stored in the first DRAM array and the second DRAM array are identical, data values are read from the conventional DRAM memory cells of the first DRAM array, instead of from the DRAM CAM cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.