Semiconductor memory device
US6563759B2 · kind B2 · utility
90Cited by
4References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Jun 4, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.