Frame synchronization and detection technique for a digital receiver
US6563856B1 · kind B1 · utility
27Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1998 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Jul 8, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W84/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A combiner circuit and method for use in a digital transmitter within a communication system. The combiner circuit receives a number of signal streams that include data frames. Each frame includes an arbitrary data sequence and portions of a unique word. The combiner circuit comprises a plurality of digital preamble circuits which append a predetermined number of contiguous bits from the unique word to each data frame. The system utilizes a plurality of spreaders, shifters, and a summer to further modify the data stream for transmission.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.