Computer method and apparatus for division and square root operations using signed digit
US6564239B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2001 |
| Grant date | May 13, 2003 |
| Priority date | — |
| Expiry date | Dec 14, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/5352
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer method and apparatus for performing a square root or division operation generating a root or quotient is presented. A partial remainder is stored in radix-2 or radix-4 signed digit format. A decoder is provided for computing a root or quotient digit, and a correction term dependent on a number of the most significant digits of the partial remainder. An adder is provided for computing the sum of the signed digit partial remainder and the correction term in binary format, and providing the result in signed digit format. The adder computes a carry out independent of a carry in bit and a sum dependent on a Carry_in bit providing a fast adder independent of carry propagate delays. The scaler performs a multiplication by two of the result output from the adder in signed digit format to provide a signed digit next partial remainder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.